1. Field of the Invention
The present invention relates to a semiconductor module and a semiconductor device using a power semiconductor element, and more particularly relates to a semiconductor device for inverter and converter.
2. Description of the Related Art
In various kind of motor control, GTOs (Gate Turn Off Thyristors) have been used in the field of large power and transistors have been used in the field of small power. However, in recent years IGBTs (Insulated Gate Bipolar Transistors) are rapidly spreading in the field of GTO and transistor because of ease of use that large current can be controlled by voltage signal. IGBTs are generally used in the form of module. Today, there are various types. For instance, in three-phase motor control, three phase and upper-arm/lower-arm currents need to be switched. That is, three switches for upper arms, three switches for lower arms, total of six switches are required. Therefore, there are a type where IGBTs corresponding to one arm are mounted on a module, a type where IGBTs corresponding to six arms are mounted on a module, and a type where an additional circuit is further mounted.
As for structures, although there are proposed various ideas, an example close to the present invention, in which IGBTs corresponding to one arm are mounted on a module, will be explained below.
Since plural chips of IGBT are used in connecting in parallel when a single chip cannot control a desired capacity of current, a semiconductor switching device mounting plural chips connected in parallel will be discussed.
A structure will be described below, according to a common manufacturing process. One surface of an IGBT chip is bonded on one of Cu thin plates, which are bonded on both surfaces of an alumina or AlN ceramic substrate, using a solder having a highest melting point among solders to be used in the module. This Cu plate commonly becomes a collector terminal. On the other surface of the chip, an emitter and a gate electrodes are formed. Both are wire-bonded to an emitter and a gate terminal Cu thin plates formed on the same surface of the ceramic substrate as the collector terminal are formed, respectively. The Cu plate on the other surface of the ceramic substrate is bonded to a cooling plate as a base of the module using solder. An Al or Cu plate is commonly used for the cooling plate. Connection of the module external terminals to the electrodes on the ceramic substrate is performed by Cu leads integrally formed together with the external terminals. The external terminal is usually called as a terminal block. A molded resin case is bonded to the metallic base (cooling plate) using an adhesive. A gel is injected through an aperture intentionally opened between the case and the terminal block and hardened, and then above it a hard resin is injected and hardened. It is basically preferable to harden the gel after sufficiently removing bubbles from the injected gel. However, if removing of bubbles is performed in this structure, the gel rises up along the inner surface of the case to cause degradation of bonding between the hard resin and the case. Therefore, the hard resin is injected without the important removal of bubbles.
The above is a common manufacturing process and a common structure of a module.
The module is attached to a proper cooling structure with bolts using holes formed on the four corners of the metallic base. Since the electric potential of the cooling structure is generally in ground potential, insulation to the IGBT chip is performed by the ceramic substrate.
The external terminals are composed of a collector terminal, an emitter terminal, a gate terminal and an emitter auxiliary terminal for gate.
In the aforementioned conventional technology, there are problems as follows.
(1) life-time of bonding solder between the metallic base and the ceramic substrate: When a module is started to operate, heat is generated and shear stress is generated in the bonding solder due to difference of linear expansion coefficients between the metallic base and the ceramic substrate. The solder is thermal-fatigued and then cracks progress inside the solder generally from the periphery to the metallic base. When the cracks are progressed to a certain degree and the thermal resistance between the IGBT chip and the metallic base is increased, the solder cracks are acceleratively progressed due to applying of positive thermal feed-back on the solder cracks and finally the module becomes incapable of operating.
(2) The gel plays a role of passivation by coating over the IGBT chip. When the hard resin allowed to flow over the gel is hardened, the chip is usually heated at nearly 150xc2x0 C. At this time, the volume of the gel is expanded by approximately 10%. In the process of cooling after completion of hardening, cracks are generated inside the gel because the contraction of the gel volume is restricted by the case and the hard resin. This phenomenon can be confirmed by observing an actual product with X-ray. If the cracks reach over the IGBT chip, the passivation effect for the chip disappears.
(3) In a case of using modules connected in parallel, the gate-emitter circuit in the input circuit forms a loop. There are some cases where an oscillation phenomenon occurs due to inductance and floating capacitance between the gates and between the emitters and input capacitance.
(4) The external terminals are generally arranged in the lateral direction of the module in order of collector terminal, emitter terminal, gate terminal and gate/emitter auxiliary terminal by structural reason. In this arrangement, however, the external wiring becomes complex and error operation probably occurs due to mutual noises when a lot of modules are mounted as an inverter. Specially in a case where the modules are applied to an inverter for vehicle, the mounting space in vertical direction should be decreased as low as possible since the inverter is installed under the floor. Therefore, the modules are preferably mounted in arranging the shorter side direction of the modules to the vertical direction. In this case, the wiring becomes complex when the conventional arrangement of the terminals is employed.
(5) In order to switching the modules at a high speed, inductances of the collector and the emitter should be decreased as small as possible.
Although the above description regarding modules is problems on a power switching device, that is basically common problems on a current control device using semiconductors.
In the conventional technology, an insulator capacitance component is generated at the portion where withdrawal or void is generated inside the solder bonding the metallic film and the insulator substrate, or at the portion where a gap is provided between the metallic film and the insulator substrate. This insulator capacitance component is connected to an insulator capacitance component due to the insulator substrate in series. When a high voltage is applied to the module is this case, a partial discharge (corona discharge) occurs in the vacant layer where the insulator capacitance component occurs. Since the partial discharge during operation of the module deteriorates the filling agent inside the module such as silicon gel, deterioration of insulation is caused at last. The partial discharge during switching causes noise, the noise causes error operation specially in a module of insulated gate type element such as IGBT.
However, when number of semiconductor elements in a module, it is difficult to make the amount of current flowing each of the elements uniform due to variation of characteristic of each elements and difference in wiring length in side the module. When the non-uniformity in current occurs among the elements, spike noise occurs due to shift in ON/OFF time among the elements during switching operation. There arises a problem in that solder or the metallic wire of one element where current is concentrated is deteriorated in a short time comparing the other elements.
An object of the present invention is to solve the aforementioned problems in the conventional technology.
(1) Means to solve the problem (1) above is not only to suppress the amount of heat generation of the IGBT chip (the same can be said for a bipolar transistor and an MOS transistor), but also to select a ceramic substrate mounting the chip and a metallic base which have linear expansion coefficients close to each other and to employ the metallic base material having a high thermal conductivity. Since the chip and the ceramic substrate are bonded with solder, the result is that it is important to match the linear expansion coefficients of the chip, the ceramic substrate and the metallic base with one another. Since the thermal coefficient of the chip is approximately 3.5xc3x9710xe2x88x926/xc2x0 C., it is suggested that Mo is used for the metallic base. However, the inventors have found that simply using Mo instead of Cu, which is conventionally used, leads three large problems.
The first problem is that a crack occurs in the ceramic at a position under a Cu thin plate on the ceramic substrate where an electrode terminal is bonded by solder. Since the linear expansion coefficients of the ceramic substrate and the Mo plate are close to each other, the thermal stress acting on the solder between the ceramic substrate and the Mo plate is decreased. That is, the ceramic substrate and the Mo plate are thermally deformed as if the both are formed of one material. Therefore, the thermal stress between the Cu thin plate on the ceramic substrate and the ceramic substrate is increased. It has been estimated from a result of thermal stress analysis that when a Cu terminal is attached onto the Cu thin plate, the thermal stress under the terminal is extremely increased much more to cause cracks in the ceramic under the Cu thin plate. Therefore, it is necessary to prevent the ceramic substrate from damage by suppressing the thermal deformation of the Cu thin plate and decreasing the thermal stress between the Cu thin plate and the ceramic substrate in such a structure that the Cu thin plate portion to be attached with the Cu terminal is not bonded to the ceramic substrate, that is, in a floating state, or that the portion to be attached with the Cu terminal is not placed in the periphery of the Cu thin plate pattern, but is placed in the inner side of the Cu thin plate pattern, or that a material having a small linear expansion coefficient such as Mo is inserted between the Cu terminal and the Cu thin plate.
The second problem is that loosening of fixing bolt or damage of fixing bolt occurs by thermal deformation due to the difference in linear expansion coefficients the metallic base of a semiconductor device and the member to fix the semiconductor device. In order to solve the problem, the thermal deformation described above is absorbed by deformation of a bolt in such a structure that the length of the bolt is lengthened by inserting a ring having a linear expansion coefficient close to that of the bolt between the head of the bolt and the metallic base.
The third problem is that there is no material of which linear expansion coefficient is close to that of silicon and thermal conductivity is as large as that of Cu. Mo does not satisfy this condition. For instance, the thermal conductivity of Cu is approximately 390 W/mK. On the other hand, the thermal conductivity of Mo is approximately 140 W/mK which is about ⅓ of that of Cu. As far as considering the thermal resistance from the chip to the metallic base, this difference does not become a problem, but grease is usually inserted between external cooling members to attach a semiconductor device in order to absorb bending of the external cooling members. However, since the thermal conductivity of grease is as low as 1 W/mK, in order to compensate the thermal resistance of the grease layer it is necessary to diffuse heat generated inside the semiconductor device over the whole area of the metallic base and then dissipate the heat from the large area through the grease layer. When Mo is used for the metallic base, the heat transferred from the chip is not sufficiently diffused and accordingly the heat has to be dissipated from a small area of the metallic base. This increases the thermal resistance. In order to avoid this phenomenon, it is necessary to arrange the heat sources of the chips as sparse as possible.
(2) In order to prevent the crack in the gel described above in the item of problem (2), it is necessary that the interface between the gel and the hard resin injected on the gel is separated when the hard resin is hardened. Although it is preferable that the surface of the gel is coated with a mold release agent, there is no proper material in the state of the art.
With this being the situation, a space is provided above the upper surface of the gel so that the gel can freely expand and contract. In this case, it is a key point to maintain the hermeticity of the space. The following structures are invented.
(i) The gap between the terminal and the mold in a terminal block is coated with a high viscous resin or a hard resin to be described (ii) below.
(ii) The case and the block are engaged with a J-shaped structure, and this portion is sealed using a hard resin.
Even if the above countermeasure for hermeticity is performed, countermeasure for condensation on the surface of the gel is required since the case and so on are made of organic materials. Thereby, the following method is invented. The terminal passes through the inside of the gel and the space. When condensation occurs on the surface of the gel, the withstanding voltage of insulation between the electrodes is degraded on the surface of the gel. Therefore, the electrode in the space is covered with the molding material for the terminal block so that the lowermost covered portion is dipped into the gel. That is, the invented structure is that the electrode inside the module is not exposed to the space.
(3) In order to suppress the oscillation phenomenon apt to occur in the parallel connection of the semiconductor device described above in the item of the problem (3), it is effective to insert an external resistor in the gate circuit. In this case, it is necessary to suppress the external noise added to the gate circuit as low as possible. The invented terminal arrangement to suppress the noise due to electromagnetic induction is that an auxiliary gate terminal is provided in the terminal block of the semiconductor switching device to decrease the area formed by the gate circuit and the wire of the auxiliary emitter circuit.
(4) As described above in the item of the problem (4), the invented structure is that the collector and the emitter terminals are arranged in the direction of the shorter side of the module in order to decrease mounting area and simplify the wiring as an inverter.
(5) As described above in order to suppress the inductance of the electrode terminal as small as possible, the following structures are invented.
(i) In order to suppress the inductance of the electrode terminal small, the mechanical length of the terminal is made as short as possible. The invented structure is that the collector and the emitter terminals are crossed with each other with spacing in the vertical direction for keeping insulation inside the gel to shorten the length of the terminals.
(ii) As an alternative method, there is a method to decrease the effective inductance utilizing the mutual inductance by considering the current flow directions of the collector and the emitter terminals. The invented structure is that in order to suppress the inductance of the electrode terminals small, the vertical wide width portions of the collector and the emitter terminals are arranged in parallel to each other since the current flows in the vertical position of the collector and the emitter terminals are opposite to each other.
The circuit board according to the present invention comprises a means for short-circuiting an insulator capacitance component which is generated at the portion where withdrawal or void is generated inside the solder bonding the metallic film and the insulator substrate, or at the portion where a gap is provided between the metallic film and the insulator substrate.
In more detail, a first conductor layer is provided on one of the surfaces of the insulator plate, and a second conductor layer is provided in a position facing to the first conductor layer on the insulator plate, consequently, the second conductor layer is provided in separating from the first conductor. Further, the first conductor layer and the second conductor layer are electrically connected by a conductor.
In the semiconductor device according to the present invention, semiconductor elements are jointed to the first conductor layer on the circuit board described above, and at the same time an insulator capacitance component is short-circuited by bonding a conductive base to the other surface of the insulator substrate, that is, to the surface in the opposite side of the first conductor layer.
The object of suppressing the partial discharge described above can be attained by filling a dielectric material in a gap between an insulator plate of a circuit board and a conductor layer in a circuit board such as DBC (Direct Bond Copper) board or a semiconductor device having such a board.
In more detail, the circuit board according to the present invention comprises an insulator plate, a conductor layer placed on the surface of the insulator plate, a dielectric layer provided in a gap portion between the insulator plate and the conductor layer. Therein, the following relationship exists among the dielectric constant of the dielectric layer ∈g, the dielectric constant of the insulator plate ∈b,the thickness of the gap portion Lg, and the thickness of the insulator plate Lb.
∈gxe2x89xa7∈bxc3x97(Lg/Lb)xe2x80x83xe2x80x83(Equation 1)
There, ∈g and ∈b are in the same unit, and Lg and Lb are also in the same unit.
In the semiconductor device according to the present invention, semiconductor elements are jointed to the conductor layer on the circuit board having the structure described above, and at the same time the circuit board is jointed to a conductive support base. Further, in the semiconductor device according to the present invention, a fluid dielectric material is filled in the device so as to adjoin to the insulator plate and the conductor layer of the circuit board contained.
The semiconductor module to attain the object described above comprises a substrate made of an insulator, a plurality of semiconductor elements arranged on the insulator substrate, external connecting terminals electrically connected to an external apparatus, a conductor pattern formed on the insulator substrate, jointed with the external connecting terminals as well as electrically connected with the electrodes of the plurality of semiconductor elements in parallel to form a current path from the external connecting terminals to the plurality of semiconductor elements, wherein the conductor pattern is formed symmetrically in regard to a certain phantom line on the insulator substrate, a plurality of positions on the phantom line and symmetrical in regard to the phantom line being used as jointing zones for the external connecting terminal, current bypass portions to make the individual current paths of the plurality of semiconductor elements in a nearly equal length being provided, the current bypass portion is formed by cutting away a path between a semiconductor element and the jointing zone and providing a bypass for allowing current to flow between the semiconductor element and the jointing zone when the distance between the electrode of the semiconductor element and the jointing zone is shorter than the distances between the electrodes of the other semiconductor elements and the jointing zones. In a case where the semiconductor element has plural electrodes or an expanded electrode, the averaged distance is taken as the distance between the electrode of the semiconductor element and the jointing zone.
Further, the semiconductor module to attain the object described above comprises a substrate made of an insulator, a plurality of semiconductor elements arranged on said insulator substrate, external connecting terminals electrically connected to an external apparatus, a conductor pattern formed on the insulator substrate, jointed with the external connecting terminals as well as electrically connected with the electrodes of the plurality of semiconductor elements in parallel to form a current path from the external connecting terminals to the plurality of semiconductor elements, wherein the external connecting terminal comprises a facing portion on the conductor pattern, the facing portion being parallel to and facing to the zone of each of the current paths for each of the semiconductor elements, the direction of current flow in the facing portion being opposite to the direction of current flow in each of the current paths.
By forming a conductor pattern symmetrical in regard to a specified phantom line as the center line and symmetrically arranging a plurality of semiconductor elements, the current path length concerning a semiconductor element on the right hand side and the current path length in relation to a semiconductor element on the left hand side become equal to each other, the inductances of the both current paths also become equal, and consequently the same current can flow both in the element on the right hand side and in the element on the left hand side. However, even if plural semiconductor elements are symmetrically arranged, for example, in a case of three semiconductor elements, the current flowing in a semiconductor placed in the center is different from the current flowing in the other semiconductor element. In more detail, in a case where number of semiconductor elements is three and the junction zone for the external connecting terminals are placed on the phantom line for symmetrical standard, the current path length concerning the semiconductor element in the center is shorter than the current path length in relation to the other semiconductor elements, the inductance of the current path in relation to the semiconductor element placed in the center is also smaller than the inductances of the current path in relation to the other semiconductor elements, and consequently current flows much in the element placed in the center.
In the present invention, a plurality of semiconductor elements are symmetrically arranged, and current bypass portions to make the individual current paths of the plurality of semiconductor elements in a nearly equal length being provided. The current bypass portion is formed by cutting away a path between a semiconductor element and the jointing zone and providing a bypass for allowing current to flow between the semiconductor element and the jointing zone when the distance between the electrode of the semiconductor element and the jointing zone is shorter than the distances between the electrodes of the other semiconductor elements and the jointing zones. As the result, the inductance of a current path in relation to a semiconductor element in which much current flows is increased and becomes equal to the inductance of the current paths in relation to the other semiconductor elements. The same quantity of current flows in each of all the semiconductor elements. In more detail, in a case of three semiconductors, a current bypass portion is formed by cutting away the conductor pattern between a semiconductor element and the jointing zone for the external connecting terminal and providing a bypass for allowing current to flow between the semiconductor element placed in the center and the jointing zone. By lengthening the current path in relation to the semiconductor element placed in the center, the length of current path becomes equal to the length of the current path in relation to the other semiconductor elements. By doing so, the same quantity of current flows in each of all the semiconductor elements.
When current flows in a pair of parallel wires in the opposite directions to each other, each of the inductance of the wire is mutually canceled. Therefore, in a case where a facing portion in facing to the conductor pattern is formed in the external connecting terminal, the inductance in the region of each of the current paths for plural semiconductor elements and the inductance in the facing portion of the external connecting terminal are mutually canceled. In this reason, even if there are differences among the lengths of current paths in the conductor pattern for the plural semiconductor elements, there is almost no difference among the inductances of the current paths and consequently the same quantity of current can be conducted in each of the semiconductor elements.
A semiconductor device, especially, a semiconductor large current switching device is subjected to large temperature difference and large number heat cycles. Therefore, the most important problem is to keep the life time against fatigue of solder bonding between the members used. The fundamental measure is to decrease the strain occurred in the solder to extend the life time against thermal fatigue by closing the linear expansion coefficients of the members used. With this measure, the three main problem described above must be overcome at a time. The long life time can be attained by performing the following three measures at a time, that is, (1) measure for crack produced in the ceramic substrate under a terminal, (2) dispersion of heat sources, (3) measure to decrease deformation of the fixing bolt. However, whether all the measures are required at a time or not is determined by the reliability required for a product. As for the resolution of the item (1), by separating the Cu thin plate under a terminal from the ceramic substrate, that is, in the state of so-called counter-beam, the Cu thin plate easily deforms so that stress does not occur between the ceramic substrate and the Cu thin plate. Another method is that the terminal is not bonded at the end portion of the Cu thin plate pattern, but at a position inside from the end portion by the distance of twice of the sum of the thickness of the terminal and the thickness of the Cu thin plate. By doing so, the problem to decrease the stress in the end portion of the Cu thin plate pattern can be solved. As a further method, a metal having a linear expansion coefficient close to that of the ceramic substrate is inserted between the terminal and the Cu thin plate. By sandwiching the Cu thin plate, the Cu thin plate burdens most part of the thermal deformation to decrease the thermal stress on the surface of the ceramic substrate under the terminal. As for the item (2), it is necessary to disperse chips generating heat at the same time by making the Cu thin plate patter on the ceramic substrate proper without degrade the electrical characteristics. As for the item (3), the key point is to decrease the stress produced in the bolt. A collar made of a material having a linear expansion coefficient nearly equal to the linear expansion coefficient of the fixing bolt is inserted between the head of bolt and the metallic base. By lengthening the length of the bolt and thermally deforming the collar, the stress produced in the bolt is decreased.
In the conventional technology, the gel crack measure is a large problem. When crack reach to the surface of a chip, the passivation effect by gel disappears. Since the main cause to produce cracks is in the structure to impede the contraction of gel, the fundamental measure is to provide a space over the gel. This method has a bad reaction. It is necessary to keep the hermeticity of the space and to keep the insulation between the terminals. It is necessary to suppress raising-up phenomenon of gel along the case wall at injecting and hardening the gel which impedes the wetness of the hard resin between the terminal and the case. The measure against this phenomenon is that the injection and hardening of the gel is performed after the injection and hardening of the hard resin. The insulation between the terminals is kept by covering the portions of the terminals exposed in the space with a molding material. By doing so, it is also possible to reduce the weight of the device.
In the circuit board according to the present invention, even if an insulating capacitance component is generated between the first conductor layer and the insulator substrate by occurrence of withdrawal or void of the solder or by providing a gap, the insulating capacitance component is short-circuited by the second conductor layer and the conductor. Therefore, since voltage is not applied to the insulating capacitance component, the partial discharge can be prevented.
Further, in the semiconductor device according to the present invention having such a circuit board, deterioration of the filler due to partial discharge and error operation of semiconductor element can be prevented. Thus, the reliability of the semiconductor device can be improved.
In the circuit board, the insulating capacitance component (Cb) by the portion of the insulator plate contacting to the gap and the insulating capacitance component (Cg) by the gap are connected in series. Therefore, when voltage (VI) is applied to the circuit board of a semiconductor device mounting the circuit board, the voltage is split into each of the insulating capacitance components. Therein, according to the present invention, since a dielectric material is filled in the gap and the insulating capacitance component of this portion is, therefore, increased, the voltage (Vg) split in the gap can be decreased (Vg=VIxc3x97Cb/(Cg+Cb)). Accordingly, the partial discharge in the gap can be suppressed.
Where Cb is proportional to ∈b/Lb, and Cg is proportional to ∈g/Lg. Therefore, when the relation expressed by the equation 1 is satisfied, Cg can be larger than Cg. Thus the partial discharge in the gap can be certainly suppressed by decreasing Vg smaller than the voltage split in the insulator plate.
Further, by filling the semiconductor device with a fluid dielectric material, the dielectric material flows into a gap in a circuit board caused by separation of a conductor layer or crack of the insulator plate. Thus the partial discharge in the gap can be suppressed.